1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to an electrically erasable and programmable read-only memory (to be referred to as an EEPROM hereinafter) having a gate electrode with a two-layered structure.
2. Description of the Related Art
A conventional electrically erasable PROM cell is classified into the following two types. That is, a cell having a two-layered polysilicon gate electrode structure including floating and control gate electrodes, and a cell having a three-layered polysilicon gate electrode structure including an erase gate electrode in addition to the floating and control gate electrodes.
The former EEPROM cell is disclosed in, e.g., IEDM TECHNICAL DIGEST. 1985, pp. 616-619, "A SINGLE TRANSISTOR EEPROM CELL AND ITS IMPLEMENTATION IN A 512K CMOS EEPROM", Satyen Mukherjee et al. This EEPROM cell is constituted by one transistor. Therefore, this EEPROM cell has a small area, and is suitable for high integration. In addition, U.S. Pat. No. 4,467,453 discloses an equivalent circuit and some of peripheral circuits in a memory cell array in which the EEPROM cells are arranged in a matrix form.
In an EEPROM cell of this type, however, when the cell is subjected to overerase upon an erasing operation of data, a threshold voltage V.sub.TH of a cell transistor is set to be negative to cause a read error. The above overerase state is caused by the following mechanism. More specifically, in the conventional EEPROM, data stored in the cell transistor is simultaneously erased in advance prior to writing data. The memory cell array before an erase operation includes a cell which stores data "0" (cell having a floating gate in which electrons are accumulated) and a cell which stores data "1" (cell having a floating gate in which electrons are not accumulated). When the stored data are simultaneously erased in the above state, excessive electrons may often be discharged from the floating gate of the cell. The state wherein excessive negative electric charges are discharged from the floating gate is equivalent to a state wherein positive charges are accumulated in the floating gate. The cell having the floating gate from which excessive electrons are discharged is a cell in the overerase state. In a cell in such an overerase state, a channel which is present in a substrate under the floating gate electrode is inverted to obtain the depletion type cell transistor. In a read mode, assume that a memory cell connected to a bit line to which the selected memory cell is connected is in the overerase state. Even if this memory cell in the overerase state is non-selected (connected to a non-selected word line), and the selected cell is in a "0" write state, it is determined that data stored in the selected cell is "1". This is caused for the following reason. The selected memory cell is not turned on. However, since the memory cell in the overerase state (normally ON) is connected to the bit line to which the selected memory cell is connected, the bit line is discharged through a current path between the drain and the source of the memory cell in the overerase state. Therefore, in order to prevent such a read error, conventionally, the discharge conditions of electrons from the floating gate in an erase mode are optimized, thus setting the threshold voltage V.sub.TH of the cell transistor after an erase operation to be positive.
As described above, however, in order to optimize the electron discharge conditions, electrons must be discharged while an amount of electrons accumulated in the floating gate is monitored. For this reason, an erase operation is complicated, and it is difficult to control the erasing of data.
The latter EEPROM cell is disclosed in NIKKEI MICRODEVICES, 1986, March, "A tendency toward a one transistor/cell EEPROM pp. 75-76".
In this EEPROM cell, a boosted high voltage is applied to an erase gate electrode upon an erase operation of stored data. According to a structure described in this literature, an offset region in which the floating gate electrode is not formed is arranged on a part of a channel region in order to prevent a read error even if a threshold voltage V.sub.TH of the cell transistor after an erase operation becomes negative due to the above-mentioned overerase state. In this offset region, the channel region is opposite to a control gate electrode via a gate insulating film, thus forming an offset MOS transistor. Even if the channel region under the floating gate electrode is inverted due to the overerase state, the channel region under the offset region is not inverted unless the cell is selected and a voltage is applied to the control gate electrode. In other words, the offset MOS transistor is not turned on unless the EEPROM cell is selected. Thus, even if the cell is in the overerase state, a current does not flow through a current path between the drain and the source. As a result, a read error can be prevented.
This EEPROM cell, however, substantially consists of two transistors. Therefore, a cell area is undesirably increased.